This invention relates to electronic devices, and more particularly to a high-speed memory-based buffer, and system and method for use thereof.
Hardware buffers are devices that receive bits from one or more devices, store the bits temporarily, and then provide the bits to other device(s). Buffers are often used to interface devices that operate at different speeds or with different sets of priorities. A buffer allows faster devices to operate on a data stream without being held up by slower devices.
One characteristic of a buffer is the size of the buffer, including the depth (i.e., the number of different data entries which can be stored concurrently) as well as the width (i.e., the number of bits that can be comprised in a single data entry).
As the speed of computer systems increases, maintaining low latency, i.e., the time required to read data from the buffer after data has been written into the buffer, is increasingly important. Thus, it is desirable to have a buffer with a large depth and a minimal latency. Preferably, the turnaround time should have no latency, that is, data entries should be accepted into the buffer on each clock cycle until the buffer can no longer accept data entries and data entries should be available to be read out on each clock cycle until the buffer is empty. The buffer should also be relatively deep and wide. In addition, it is desirable that the buffer protect against data corruption.
One embodiment of the invention is a buffer, having a first buffer input, a second buffer input, and a buffer output. The buffer is configured to store a plurality of data entries. The buffer includes: a first memory, the first memory having an input and an output. The input of the first memory is coupled to the first buffer input. The buffer also includes a second memory. The second memory has an input and an output. The input of the second memory is coupled to the second buffer input. The buffer also includes a first register. The first register has an input and an output. The input of the first register is coupled to the first buffer input, the second buffer input, the output of the first memory, and the output of the second memory. The output of the first register is coupled to the buffer output. The buffer also includes a second register configured to store a second data entry. The second register has an input and an output. The input of the second register is coupled to the first buffer input, the second buffer input, the output of the first memory, and the output of the second memory. The output of the second register is coupled to the input of the first register.